In a traditional SAR ADC a switched capacitor DAC is coupled to a comparator having an output coupled to a successive approximation register controlling non-overlapping switch drivers coupled to the switched capacitor DAC. An analog input sample-and-hold is provided, which may be switched capacitor DAC itself, with the overall SAR ADC being controlled by a controller, such as a state machine.
In operation, the capacitor DAC output is switched to ground and the capacitors are all simultaneously connected to and charged to the analog input voltage in the analog input sample-and-hold circuit. Then the grounding is removed and each capacitor is coupled to a reference voltage, one at a time, starting from the most significant bit (MSB). Typically, the capacitance representing the least significant bit (LSB) is replicated so that the capacitance of the MSB is equal to the sum of all the rest of the capacitances. Thus, when the switch drivers connect the capacitance associated with the MSB to the reference voltage, the comparator will reverse state if the analog input voltage is less than half the reference voltage Vref, but will not reverse state if it is more than half of the Vref. If the comparator does reverse state, then the non-overlapping switch driver associated with the MSB is reset. In any event, the comparator output will remain or return to its original state.
Then the non-overlapping switch driver is set, and left set if the output of the converter does not change, or reset if the output of the comparator does change, again after which the comparator will remain or return to its original state again. This sequence is repeated until the LSB is tested, after which latches in the SAR controlling the non-overlapping switch drivers will contain the digital value of the analog input signal held in the analog input sample-and-hold. Each latch in SAR is set before the respective switch driver is initiated, and if the comparator output changes state, each latch must be reset before the switch drivers are themselves reset. In addition, the output of successive approximation register may go through a thermometric encoder to improve differential-non-linearity (DNL) in the outputted data before being applied to the switched capacitor DAC. For example, a typical 5 to 31 segmented thermometric encoder along with the SAR register in a 0.35 micron process can introduce a delay of about 3 nanoseconds.
It can be seen from the above operation that the digital path in SAR ADC is normally limited by the sum of the delays introduced through the switched capacitor DAC, comparator, the successive approximation register, and the thermometric encoder. Such delays can be substantial, especially, when the sequence is repeated in a non-overlapping fashion for each successive bit in each multiple bit conversion. Any such delays in the digital path of serial SAR ADCs can significantly affect data throughput rate.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.